1. Field of the Invention
The present invention relates to a matrix-type image display device such as liquid crystal panel and, more particularly, to a frame data compensation amount output device, a frame data compensation device, a frame data display device, a vertical edge detector and a vertical edge level signal output device for the purpose of improving rate-of-change of a gradation, and a frame data compensation output method, a frame data compensation method, a frame data display method, a vertical edge detection method and a vertical edge level output method.
2. Description of the Related Art
Prior Art 1.
In the conventional liquid crystal panel, an image memory that stores one frame of digital image data is provided. Further, a comparison circuit that compares levels of the above-mentioned digital image data and an image data to be read out one frame later from the above-mentioned image memory to output a change in gradation signal is also provided. In the case where this comparison circuit determines that levels of both of these comparison data are the same, the comparison circuit selects a normal liquid crystal drive voltage, and drives displaying electrode of a liquid crystal panel. On the contrary, in the case where the comparison circuit determines that levels of both of the above-mentioned comparison data are not the same, the comparison circuit selects a liquid crystal drive voltage higher than the above-mentioned normal liquid crystal drive voltage, and drives displaying electrode of a liquid crystal panel, as disclosed in, for example, the Japanese Patent Publication (unexamined) No. 189232/1994, at FIG. 2.
Prior Art 2.
In the conventional liquid crystal panel, in the case where an input signal is an interlace (interlaced scan) signal such as TV signal, a sequential scan conversion circuit that converts an interlace signal to a progressive (sequential scan) signal, is combined to carry out a further compensation of a drive voltage of the liquid crystal panel having been transformed larger than usual at the time of the change in gradation. Consequently, display performance on the liquid crystal panel at the time of inputting any interlace signal is improved, as disclosed in the Japanese Patent Publication (unexamined) No. 288589/1992, at FIGS. 16 and 15.
As shown in the above-mentioned Prior art 1, it is certainly possible to improve rate of change in gradation by increasing response rate of the liquid crystal panel. Such increase in response rate can be achieved by making a drive voltage of the liquid crystal at the time of change in gradation larger than normal liquid crystal drive voltage.
However, in the case where input signal is an interlace signal, for example, NTSC signal, a flicker interference (flickering) as aliasing interference brought about by the sampling theorem is contained in a region where a vertical frequency component is high. Moreover, this interference component is an interference the gradation of which varies every frame. Accordingly, since this interference component is also emphasized by a signal processing as shown in the above-mentioned prior art 1, a problem exists in that quality level of a video picture to be displayed on the liquid crystal panel is deteriorated.
In the above-mentioned prior art 2, in the case where input signal is an interlace (interlaced scan) signal such as TV signal, a sequential scan conversion circuit that converts the interlace signal to a progressive (sequential scan) signal, is incorporated. Then, a drive voltage of the liquid crystal panel having been transformed to be larger than usual at the time of change in gradation is further compensated thereby improving a display performance on the liquid crystal panel when an interlace signal is inputted. In addition, a drive voltage of the liquid crystal at the time of change in gradation is made larger than a normal drive voltage. Thus, the rate-of-change in gradation is improved by speeding up a response rate of the liquid crystal.
However, in the above-mentioned prior art 2, since it becomes necessary to be provided with various circuits such as frame memory accompanied by the addition of a sequential scan conversion circuit, a problem exists in that a circuit scale constituting the device grows in size as compared with the prior art 1.
Furthermore, an input signal is limited to the case of an interlace signal in the above-mentioned prior art 2. Thus, another problem exits in that, in the case of outputting a signal (progressive signal) after having processed an input interlace signal in which an interference component such as flicker interference remains contained as is a home computer provided with, e.g., TV tuner, it is impossible to effectively cope with the case.